Elioenai, please address my post.
I'd be curious to read up on this, got a link?
I don't have a paper, but I can give a simple explanation.
The idea is that transistors are made of structures formed from atoms (as are all things, really). The specific structures in question form basically bridges and platforms along which electrons travel.
In the things with which we interact on a daily basis, this is not a problem. The atoms are so small that granularity is not an issue. However, as you get smaller and smaller, this becomes more and more of an issue.
In the first computer I could call "my own", transistors were built on what is called a 0.13 micrometer process (130nm). This isn't really an uber-technical or uber-specific term, but it's one that the enthusiast and technical computer communities use. It gives a rough indication of how big various structures should be, and it (more importantly for this) can be compared to other sizes when used within the same company. Now, 130nm is tiny, when you think about it. For reference, a red blood cell is around 8000nm across on average, viruses average somewhere around the 50-100nm mark, and the atomic radius of a silicon atom (which is a major component of electronics) is around 0.11nm.
It was only around 9-10 years ago that people on the cutting edge were using this manufacturing process to make their chips. Now, people have spread out a bit more as rising costs (which is a result of what I'm outlining in this post) mean that larger transistor sizes are becoming more cost efficient compared to the cost of switching to the smaller manufacturing processes. But Samsung uses predominantly a 32nm process, Global Foundries (which makes chips for AMD) uses 32nm, TSMC (which also make chips for AMD, as well as NVIDIA and soon to be Apple) use a 28nm process, and Intel is currently using a 22nm process (transitioning to 14nm). This is partly the reason why Intel is so strong today - they have the volume and price margins which allow them to dump literally billions of dollars into manufacturing R&D every year, which allows them to make faster, more power efficient chips, which gives them margins and volume, which gives them R&D money, which...etc.
Note that those different numbers don't really mean jack. This information is very closely guarded, but in almost all likelihood the 32nm Samsung and Global Foundries processes won't be exactly the same size. As I said before, comparisons between different process sizes aren't that useful between companies. Suffice it to say that they're
roughly the same size.
The whole idea of moving to a smaller process is that not only do you get to fit more chips into the same area, but because the structures are smaller you need lower voltages to switch the transistors on and off. And because of high-school level physics, P=VI and V=IR, keeping resistance the same (it's not in real life, but it's a reasonable simplification) power is proportional to voltage squared. Having lower-power chips means you get them in laptops, tablets, phones, and basically everything that drives modern civilization. The rate at which they get smaller was first formed into Moore's Law (more of a guideline) by Gordon Moore (co-founder of Intel). He predicted that every 18 months, transistor density would double - since the only way is to make them smaller at the moment, that's the way they've been going: smaller.
Intel's current roadmaps outline a production of 14nm chips starting this year, 10nm in 2015, 7nm in 2017, and 5nm in 2019 (going off current trends - Intel has this whole tick tock thing going which makes their roadmaps super rigid and easy to predict). Now, most of the major semiconductor manufacturing companies (we call them fabs) have had troubles migrating to the smaller processes. Intel had trouble migrating from 45nm to 32nm, they had to develop a completely new way of building transistors to get from 32nm to 22nm and beyond, and there have been rumoured to be a few small troubles going from 22 to 14nm and beyond. TSMC had so much trouble with 32nm that they had to abandon that entirely and go straight to 28nm. At the moment there is a lot of speculation in general about when transistors will stop getting smaller at the rate they are - basically, when Moore's Law will break.
The thing is, that as you get smaller and smaller, aforementioned granularity becomes more apparent. 5nm is only about 40-50 Si atoms across. Some of the vias, sources, and sinks in the transistor itself will be significantly smaller. And as this granularity becomes more apparent, it becomes more and more important to make structures a precise number of atoms across, which makes producing the transistors that much harder. Current chips are made with a certain amount of variability - fabs give chip designers certain requirements for variability and redundancy they need to make sure the chip works when it's built, and smaller processes require less variability and more redundancy. Not to mention that due to the way that fixed vs variable costs work in manufacturing (most of the costs now are fixed - and they are huge) it becomes less and less feasible to transition to newer process nodes each time because you get less profit before you need to switch again, not to mention each node requires more and more R&D money to implement. It doesn't take a genius to figure out that this is an untenable situation and something has to break sometime down the line.
Another limitation of smaller things is that quantum effects become more apparent. The whole working premise of a transistor is that some of the time it has to keep some electrons from going places we don't want it to go. Quantum mechanics means that at these scales, tunneling through the dielectric material becomes a real nuisance, and as a result, transistors may turn on when they're not supposed to. Worse, we have no way of predicting where and when this will happen in the chip (there are billions of transistors in modern high-end chips, and this is only going to increase). The only thing we can do is build with this as an inevitability and try to mitigate it as much as possible - which aside from wasting valuable engineer time, kind of mitigates the advantage of going to a smaller process node in the first place.
There are alternatives being researched. IBM is currently going with carbon nanotube transistors, among other solutions (IBM is a company known to have fingers in many, many pies). Various other companies with R&D budgets and a vested interest in the computer industry, such as Intel, AMD, and HP, are researching their own solutions. So far, because of the steadiness of Moore's Law, none of these have yet seen light of day because individual labs working on experimental products can't keep up with the rate of silicon semiconductor progress. In the future though, that may change.
Anyone else with anything to add should chime in with corrections or addenda. I'm not an industry expert or a professional in the area, I'm just an enthusiast with an interest in this kind of thing. If you want more information, Wikipedia has a lot good articles that together paint the kind of picture and provide a good groundwork for what I've talked about. There are also a few very good tech sites that I read which discuss issues like this (this is going completely off topic, but most "tech" sites are designed with typical consumers in mind, and are frankly too vague and waffly for my liking). Anandtech is very good, and realworldtech is likewise very good (though it's updated only once every few weeks/months). Another good site is dailytech, though they're more general-science based - but they still have very good quality articles. Take a look at the article archives of these sites, there will be articles covering this kind of thing.
Yeah, I know. This is really off topic. But I like this kind of thing
EDIT: Wow. This is nearly 1500 words. You'd better appreciate this.